library ieee;
 use ieee.std_logic_1164.all;
 use ieee.std_logic_unsigned.all;
 use ieee.std_logic_arith.all;
 use ieee.math_real.all; 
 use ieee.numeric_std.all;

library work;
    use work.router_pack.all;
    use work.env_pack.all;
    
-------------------------------------------------------------------------

entity environment is
end environment;

-------------------------------------------------------------------------

architecture environment_arch of environment is

-- Environment Components --

component module
port(
   -- General Signals: --
   RESET   		: in std_logic;
   MODULE_ID	   : in std_logic_vector(2*e_coord_position_width_c-1 downto 0);
   BASE_CLK     : in std_logic;
   CLOCK_MULT   : in std_logic_vector(e_clock_mult_width_c-1 downto 0);
   
   -- Input Port i/f: --
   RI      : in std_logic;
   AI      : out std_logic;
   DI      : in std_logic_vector(flit_size_c-1 downto 0);
       
   -- Output Port i/f: --
   RO      : out std_logic;
   AO      : in std_logic;
   DO      : out std_logic_vector(flit_size_c-1 downto 0);
   
   -- Environment Settings --
    WORKLOAD          : in std_logic_vector(e_workload_width_c-1 downto 0);
    MAX_VC            : in std_logic_vector(vc_width-1 downto 0);
    MAX_SL            : in std_logic_vector(msl_ind_width-1 downto 0);
    MAX_PACKET_SIZE   : in std_logic_vector(e_packet_size_width_c-1 downto 0);
    MIN_PACKET_SIZE   : in std_logic_vector(e_packet_size_width_c-1 downto 0);
    SEED1             : in std_logic_vector(e_seed_width_c-1 downto 0);
    SEED2             : in std_logic_vector(e_seed_width_c-1 downto 0)
);    
end component;    

component msl_router
port(
       -- General Signlas: --
       RESET           : in  std_logic; 
       
       -- Input Ports i/f: --
       RI              : in  std_logic_vector(num_of_ports_con downto 0);
       AI              : out std_logic_vector(num_of_ports_con downto 0);
       --DI              : in  msl_router_mult_ports_data_bus_type;
       DI              : in  std_logic_vector(flit_size_c*5-1 downto 0);
       
       -- Output Ports i/f: --
       RO              : out std_logic_vector(num_of_ports_con downto 0);
       AO              : in  std_logic_vector(num_of_ports_con downto 0);
       --DO              : out msl_router_mult_ports_data_bus_type
       DO              : out std_logic_vector(flit_size_c*5-1 downto 0)
);    
end component;

-- Internal Signals --

signal       RESET         : std_logic := '1'; 
signal       BASE_CLK      : std_logic := '0';
signal       CLOCK_MULT_00 : std_logic_vector(e_clock_mult_width_c-1 downto 0) := "001";
signal       CLOCK_MULT_01 : std_logic_vector(e_clock_mult_width_c-1 downto 0) := "010";
signal       CLOCK_MULT_10 : std_logic_vector(e_clock_mult_width_c-1 downto 0) := "011";
signal       CLOCK_MULT_11 : std_logic_vector(e_clock_mult_width_c-1 downto 0) := "100";

-- Router Ports --
signal       RI_R00   :   std_logic_vector(num_of_ports_con downto 0);
signal       AI_R00   :   std_logic_vector(num_of_ports_con downto 0);
--signal       DI_00   :   msl_router_mult_ports_data_bus_type;
signal       DI_R00   :   std_logic_vector(flit_size_c*5-1 downto 0);
       
signal       RO_R00   :   std_logic_vector(num_of_ports_con downto 0);
signal       AO_R00   :   std_logic_vector(num_of_ports_con downto 0);
--signal       DO_00   :   msl_router_mult_ports_data_bus_type;
signal       DO_R00   :   std_logic_vector(flit_size_c*5-1 downto 0);

signal       RI_R01   :   std_logic_vector(num_of_ports_con downto 0);
signal       AI_R01   :   std_logic_vector(num_of_ports_con downto 0);
--signal       DI_01   :   msl_router_mult_ports_data_bus_type;
signal       DI_R01   :   std_logic_vector(flit_size_c*5-1 downto 0);
       
signal       RO_R01   :   std_logic_vector(num_of_ports_con downto 0);
signal       AO_R01   :   std_logic_vector(num_of_ports_con downto 0);
--signal       DO_01   :   msl_router_mult_ports_data_bus_type;
signal       DO_R01   :   std_logic_vector(flit_size_c*5-1 downto 0);

signal       RI_R10   :   std_logic_vector(num_of_ports_con downto 0);
signal       AI_R10   :   std_logic_vector(num_of_ports_con downto 0);
--signal       DI_10   :   msl_router_mult_ports_data_bus_type;
signal       DI_R10   :   std_logic_vector(flit_size_c*5-1 downto 0);
       
signal       RO_R10   :   std_logic_vector(num_of_ports_con downto 0);
signal       AO_R10   :   std_logic_vector(num_of_ports_con downto 0);
--signal       DO_10   :   msl_router_mult_ports_data_bus_type;
signal       DO_R10   :   std_logic_vector(flit_size_c*5-1 downto 0);

signal       RI_R11   :   std_logic_vector(num_of_ports_con downto 0);
signal       AI_R11   :   std_logic_vector(num_of_ports_con downto 0);
--signal       DI_11   :   msl_router_mult_ports_data_bus_type;
signal       DI_R11   :   std_logic_vector(flit_size_c*5-1 downto 0);
       
signal       RO_R11   :   std_logic_vector(num_of_ports_con downto 0);
signal       AO_R11   :   std_logic_vector(num_of_ports_con downto 0);
--signal       DO_11   :   msl_router_mult_ports_data_bus_type;
signal       DO_R11   :   std_logic_vector(flit_size_c*5-1 downto 0);

-- Router Ports --
alias DI_R00_P0: std_logic_vector(flit_size_c-1 downto 0) is DI_R00(flit_size_c*5-1 downto flit_size_c*4);
alias DI_R00_P1: std_logic_vector(flit_size_c-1 downto 0) is DI_R00(flit_size_c*4-1 downto flit_size_c*3);
alias DI_R00_P2: std_logic_vector(flit_size_c-1 downto 0) is DI_R00(flit_size_c*3-1 downto flit_size_c*2);
alias DI_R00_P3: std_logic_vector(flit_size_c-1 downto 0) is DI_R00(flit_size_c*2-1 downto flit_size_c*1);
alias DI_R00_P4: std_logic_vector(flit_size_c-1 downto 0) is DI_R00(flit_size_c*1-1 downto 0);

alias DO_R00_P0: std_logic_vector(flit_size_c-1 downto 0) is DO_R00(flit_size_c*5-1 downto flit_size_c*4);
alias DO_R00_P1: std_logic_vector(flit_size_c-1 downto 0) is DO_R00(flit_size_c*4-1 downto flit_size_c*3);
alias DO_R00_P2: std_logic_vector(flit_size_c-1 downto 0) is DO_R00(flit_size_c*3-1 downto flit_size_c*2);
alias DO_R00_P3: std_logic_vector(flit_size_c-1 downto 0) is DO_R00(flit_size_c*2-1 downto flit_size_c*1);
alias DO_R00_P4: std_logic_vector(flit_size_c-1 downto 0) is DO_R00(flit_size_c*1-1 downto 0);

alias DI_R01_P0: std_logic_vector(flit_size_c-1 downto 0) is DI_R01(flit_size_c*5-1 downto flit_size_c*4);
alias DI_R01_P1: std_logic_vector(flit_size_c-1 downto 0) is DI_R01(flit_size_c*4-1 downto flit_size_c*3);
alias DI_R01_P2: std_logic_vector(flit_size_c-1 downto 0) is DI_R01(flit_size_c*3-1 downto flit_size_c*2);
alias DI_R01_P3: std_logic_vector(flit_size_c-1 downto 0) is DI_R01(flit_size_c*2-1 downto flit_size_c*1);
alias DI_R01_P4: std_logic_vector(flit_size_c-1 downto 0) is DI_R01(flit_size_c*1-1 downto 0);

alias DO_R01_P0: std_logic_vector(flit_size_c-1 downto 0) is DO_R01(flit_size_c*5-1 downto flit_size_c*4);
alias DO_R01_P1: std_logic_vector(flit_size_c-1 downto 0) is DO_R01(flit_size_c*4-1 downto flit_size_c*3);
alias DO_R01_P2: std_logic_vector(flit_size_c-1 downto 0) is DO_R01(flit_size_c*3-1 downto flit_size_c*2);
alias DO_R01_P3: std_logic_vector(flit_size_c-1 downto 0) is DO_R01(flit_size_c*2-1 downto flit_size_c*1);
alias DO_R01_P4: std_logic_vector(flit_size_c-1 downto 0) is DO_R01(flit_size_c*1-1 downto 0);

alias DI_R10_P0: std_logic_vector(flit_size_c-1 downto 0) is DI_R10(flit_size_c*5-1 downto flit_size_c*4);
alias DI_R10_P1: std_logic_vector(flit_size_c-1 downto 0) is DI_R10(flit_size_c*4-1 downto flit_size_c*3);
alias DI_R10_P2: std_logic_vector(flit_size_c-1 downto 0) is DI_R10(flit_size_c*3-1 downto flit_size_c*2);
alias DI_R10_P3: std_logic_vector(flit_size_c-1 downto 0) is DI_R10(flit_size_c*2-1 downto flit_size_c*1);
alias DI_R10_P4: std_logic_vector(flit_size_c-1 downto 0) is DI_R10(flit_size_c*1-1 downto 0);

alias DO_R10_P0: std_logic_vector(flit_size_c-1 downto 0) is DO_R10(flit_size_c*5-1 downto flit_size_c*4);
alias DO_R10_P1: std_logic_vector(flit_size_c-1 downto 0) is DO_R10(flit_size_c*4-1 downto flit_size_c*3);
alias DO_R10_P2: std_logic_vector(flit_size_c-1 downto 0) is DO_R10(flit_size_c*3-1 downto flit_size_c*2);
alias DO_R10_P3: std_logic_vector(flit_size_c-1 downto 0) is DO_R10(flit_size_c*2-1 downto flit_size_c*1);
alias DO_R10_P4: std_logic_vector(flit_size_c-1 downto 0) is DO_R10(flit_size_c*1-1 downto 0);

alias DI_R11_P0: std_logic_vector(flit_size_c-1 downto 0) is DI_R11(flit_size_c*5-1 downto flit_size_c*4);
alias DI_R11_P1: std_logic_vector(flit_size_c-1 downto 0) is DI_R11(flit_size_c*4-1 downto flit_size_c*3);
alias DI_R11_P2: std_logic_vector(flit_size_c-1 downto 0) is DI_R11(flit_size_c*3-1 downto flit_size_c*2);
alias DI_R11_P3: std_logic_vector(flit_size_c-1 downto 0) is DI_R11(flit_size_c*2-1 downto flit_size_c*1);
alias DI_R11_P4: std_logic_vector(flit_size_c-1 downto 0) is DI_R11(flit_size_c*1-1 downto 0);

alias DO_R11_P0: std_logic_vector(flit_size_c-1 downto 0) is DO_R11(flit_size_c*5-1 downto flit_size_c*4);
alias DO_R11_P1: std_logic_vector(flit_size_c-1 downto 0) is DO_R11(flit_size_c*4-1 downto flit_size_c*3);
alias DO_R11_P2: std_logic_vector(flit_size_c-1 downto 0) is DO_R11(flit_size_c*3-1 downto flit_size_c*2);
alias DO_R11_P3: std_logic_vector(flit_size_c-1 downto 0) is DO_R11(flit_size_c*2-1 downto flit_size_c*1);
alias DO_R11_P4: std_logic_vector(flit_size_c-1 downto 0) is DO_R11(flit_size_c*1-1 downto 0);

-- Module Ports --
signal RI_M00   : std_logic;
signal AI_M00   : std_logic;
signal DI_M00   : std_logic_vector(flit_size_c-1 downto 0);
signal MOD_ID_M00   : std_logic_vector(2*e_coord_position_width_c-1 downto 0);

signal RO_M00   : std_logic;
signal AO_M00   : std_logic;
signal DO_M00   : std_logic_vector(flit_size_c-1 downto 0);

signal RI_M01   : std_logic;
signal AI_M01   : std_logic;
signal DI_M01   : std_logic_vector(flit_size_c-1 downto 0);
signal MOD_ID_M01   : std_logic_vector(2*e_coord_position_width_c-1 downto 0);

signal RO_M01   : std_logic;
signal AO_M01   : std_logic;
signal DO_M01   : std_logic_vector(flit_size_c-1 downto 0);

signal RI_M10   : std_logic;
signal AI_M10   : std_logic;
signal DI_M10   : std_logic_vector(flit_size_c-1 downto 0);
signal MOD_ID_M10   : std_logic_vector(2*e_coord_position_width_c-1 downto 0);

signal RO_M10   : std_logic;
signal AO_M10   : std_logic;
signal DO_M10   : std_logic_vector(flit_size_c-1 downto 0);

signal RI_M11   : std_logic;
signal AI_M11   : std_logic;
signal DI_M11   : std_logic_vector(flit_size_c-1 downto 0);
signal MOD_ID_M11   : std_logic_vector(2*e_coord_position_width_c-1 downto 0);

signal RO_M11   : std_logic;
signal AO_M11   : std_logic;
signal DO_M11   : std_logic_vector(flit_size_c-1 downto 0);

signal M00_Seed1 : std_logic_vector(e_seed_width_c-1 downto 0);
signal M01_Seed1 : std_logic_vector(e_seed_width_c-1 downto 0);
signal M10_Seed1 : std_logic_vector(e_seed_width_c-1 downto 0);
signal M11_Seed1 : std_logic_vector(e_seed_width_c-1 downto 0);
signal M00_Seed2 : std_logic_vector(e_seed_width_c-1 downto 0);
signal M01_Seed2 : std_logic_vector(e_seed_width_c-1 downto 0);
signal M10_Seed2 : std_logic_vector(e_seed_width_c-1 downto 0);
signal M11_Seed2 : std_logic_vector(e_seed_width_c-1 downto 0);

signal env_workload_R00          : std_logic_vector(e_workload_width_c-1 downto 0);
signal env_workload_R01          : std_logic_vector(e_workload_width_c-1 downto 0);
signal env_workload_R10          : std_logic_vector(e_workload_width_c-1 downto 0);
signal env_workload_R11          : std_logic_vector(e_workload_width_c-1 downto 0);

signal env_max_vc            : std_logic_vector(vc_width-1 downto 0);
signal env_max_sl            : std_logic_vector(msl_ind_width-1 downto 0);
signal env_max_packet_size   : std_logic_vector(e_packet_size_width_c-1 downto 0);
signal env_min_packet_size   : std_logic_vector(e_packet_size_width_c-1 downto 0);


-- Environment Implementation --
begin

	seed_gen: process (RESET)
	variable randNum : real;
	variable temp_seed00_1 : real;
	variable temp_seed01_1 : real;
	variable temp_seed10_1 : real;
	variable temp_seed11_1 : real;
	variable temp_seed00_2 : real;
	variable temp_seed01_2 : real;
	variable temp_seed10_2 : real;
	variable temp_seed11_2 : real;
	variable env_seed1		   : integer := inj_rand_base_seed1_c;
	variable env_seed2		   : integer := inj_rand_base_seed2_c;
	begin
		if(RESET'event) and (RESET='0') then
			uniform(env_seed1,env_seed2,randNum);
			temp_seed00_1 := randNum * real(2 ** e_seed_width_c);
			temp_seed00_1 := floor(temp_seed00_1);
			M00_Seed1 <= conv_std_logic_vector(integer(temp_seed00_1), e_seed_width_c);
			
			uniform(env_seed1,env_seed2,randNum);
			temp_seed01_1 := randNum * real(2 ** e_seed_width_c);
			temp_seed01_1 := floor(temp_seed01_1);
			M01_Seed1 <= conv_std_logic_vector(integer(temp_seed01_1), e_seed_width_c);
			
			uniform(env_seed1,env_seed2,randNum);
			temp_seed10_1 := randNum * real(2 ** e_seed_width_c);
			temp_seed10_1 := floor(temp_seed10_1);
			M10_Seed1 <= conv_std_logic_vector(integer(temp_seed10_1), e_seed_width_c);
			
			uniform(env_seed1,env_seed2,randNum);
			temp_seed11_1 := randNum * real(2 ** e_seed_width_c);
			temp_seed11_1 := floor(temp_seed11_1);
			M11_Seed1 <= conv_std_logic_vector(integer(temp_seed11_1), e_seed_width_c);
			
			uniform(env_seed1,env_seed2,randNum);
			temp_seed00_2 := randNum * real(2 ** e_seed_width_c);
			temp_seed00_2 := floor(temp_seed00_2);
			M00_Seed2 <= conv_std_logic_vector(integer(temp_seed00_2), e_seed_width_c);
			
			uniform(env_seed1,env_seed2,randNum);
			temp_seed01_2 := randNum * real(2 ** e_seed_width_c);
			temp_seed01_2 := floor(temp_seed01_2);
			M01_Seed2 <= conv_std_logic_vector(integer(temp_seed01_2), e_seed_width_c);
			
			uniform(env_seed1,env_seed2,randNum);
			temp_seed10_2 := randNum * real(2 ** e_seed_width_c);
			temp_seed10_2 := floor(temp_seed10_2);
			M10_Seed2 <= conv_std_logic_vector(integer(temp_seed10_2), e_seed_width_c);
			
			uniform(env_seed1,env_seed2,randNum);
			temp_seed11_2 := randNum * real(2 ** e_seed_width_c);
			temp_seed11_2 := floor(temp_seed11_2);
			M11_Seed2 <= conv_std_logic_vector(integer(temp_seed11_2), e_seed_width_c);
		end if;
	end process;

    -- Environment configuration --
    
    env_workload_R00 <= conv_std_logic_vector(e_workload_R00_c,e_workload_width_c); 
    env_workload_R01 <= conv_std_logic_vector(e_workload_R01_c,e_workload_width_c);
    env_workload_R10 <= conv_std_logic_vector(e_workload_R10_c,e_workload_width_c);
    env_workload_R11 <= conv_std_logic_vector(e_workload_R11_c,e_workload_width_c);
    
    CLOCK_MULT_00 <= conv_std_logic_vector(e_clock_mult_R00_c, e_clock_mult_width_c);
    CLOCK_MULT_01 <= conv_std_logic_vector(e_clock_mult_R01_c, e_clock_mult_width_c);
    CLOCK_MULT_10 <= conv_std_logic_vector(e_clock_mult_R10_c, e_clock_mult_width_c);
    CLOCK_MULT_11 <= conv_std_logic_vector(e_clock_mult_R11_c, e_clock_mult_width_c);
    
    env_max_vc <= conv_std_logic_vector(e_max_vc_c,vc_width);
    env_max_sl <= conv_std_logic_vector(e_max_sl_c,msl_ind_width);
    env_max_packet_size <= conv_std_logic_vector(e_max_flit_count_c,e_packet_size_width_c);
    env_min_packet_size <= conv_std_logic_vector(e_min_flit_count_c,e_packet_size_width_c);
    
    -- Constant values of Module ID's    
    
    MOD_ID_M00 <= "00";
    MOD_ID_M01 <= "01";
    MOD_ID_M10 <= "10";
    MOD_ID_M11 <= "11";

    BASE_CLK <= not BASE_CLK after e_base_clock_wait_c;
    
    	reset_gen: process(AO_R00, BASE_CLK)
    	variable ao_var		      : std_logic_vector(num_of_ports_con downto 0);
    	begin
		ao_var := AO_R00;
 		if (ao_var = "00000") then
 			RESET <= '0' after e_base_clock_wait_c * (2 * (2 ** e_clock_mult_width_c));
    		end if;
    	end process;
   
    
    -- Environment interconnectivity --
    
u_msl_router_00: msl_router
port map(
       RESET           => RESET, 
       
       RI              => RI_R00,
       AI              => AI_R00,
       DI              => DI_R00,
       
       RO              => RO_R00,
       AO              => AO_R00,
       DO              => DO_R00
);

u_msl_router_01: msl_router
port map(
       RESET           => RESET, 
       
       RI              => RI_R01,
       AI              => AI_R01,
       DI              => DI_R01,
       
       RO              => RO_R01,
       AO              => AO_R01,
       DO              => DO_R01
);

u_msl_router_10: msl_router
port map(
       RESET           => RESET, 
       
       RI              => RI_R10,
       AI              => AI_R10,
       DI              => DI_R10,
       
       RO              => RO_R10,
       AO              => AO_R10,
       DO              => DO_R10
);

u_msl_router_11: msl_router
port map(
       RESET           => RESET, 
       
       RI              => RI_R11,
       AI              => AI_R11,
       DI              => DI_R11,
       
       RO              => RO_R11,
       AO              => AO_R11,
       DO              => DO_R11
);
    
u_module_00: module
port map(
       RESET      => RESET,
       MODULE_ID  => MOD_ID_M00,
       BASE_CLK   => BASE_CLK,	
       CLOCK_MULT => CLOCK_MULT_00,
   
       RI      => RI_M00,
       AI      => AI_M00,
       DI      => DI_M00,
       
       RO      => RO_M00,
       AO      => AO_M00,
       DO      => DO_M00,
       
       WORKLOAD        => env_workload_R00,
       MAX_VC          => env_max_vc,
       MAX_SL          => env_max_sl,
       MAX_PACKET_SIZE => env_max_packet_size,
       MIN_PACKET_SIZE => env_min_packet_size,
       SEED1		       => M00_Seed1,
       SEED2		       => M00_Seed2
);

u_module_01: module
port map(
       RESET      => RESET,
       MODULE_ID  => MOD_ID_M01,
       BASE_CLK   => BASE_CLK,	
       CLOCK_MULT => CLOCK_MULT_01,
       
       RI      => RI_M01,
       AI      => AI_M01,
       DI      => DI_M01,
       
       RO      => RO_M01,
       AO      => AO_M01,
       DO      => DO_M01,
       
       WORKLOAD        => env_workload_R01,
       MAX_VC          => env_max_vc,
       MAX_SL          => env_max_sl,
       MAX_PACKET_SIZE => env_max_packet_size,
       MIN_PACKET_SIZE => env_min_packet_size,
       SEED1		       => M01_Seed1,
       SEED2		       => M01_Seed2
);

u_module_10: module
port map(
       RESET      => RESET,
       MODULE_ID  => MOD_ID_M10,
       BASE_CLK   => BASE_CLK,	
       CLOCK_MULT => CLOCK_MULT_10,
       
       RI      => RI_M10,
       AI      => AI_M10,
       DI      => DI_M10,
       
       RO      => RO_M10,
       AO      => AO_M10,
       DO      => DO_M10,
       
       WORKLOAD        => env_workload_R10,
       MAX_VC          => env_max_vc,
       MAX_SL          => env_max_sl,
       MAX_PACKET_SIZE => env_max_packet_size,
       MIN_PACKET_SIZE => env_min_packet_size,
       SEED1		       => M10_Seed1,
       SEED2		       => M10_Seed2
);

u_module_11: module
port map(
       RESET      => RESET,
       MODULE_ID  => MOD_ID_M11,
       BASE_CLK   => BASE_CLK,	
       CLOCK_MULT => CLOCK_MULT_11,
       
       RI      => RI_M11,
       AI      => AI_M11,
       DI      => DI_M11,
       
       RO      => RO_M11,
       AO      => AO_M11,
       DO      => DO_M11,
       
       WORKLOAD        => env_workload_R11,
       MAX_VC          => env_max_vc,
       MAX_SL          => env_max_sl,
       MAX_PACKET_SIZE => env_max_packet_size,
       MIN_PACKET_SIZE => env_min_packet_size,
       SEED1		       => M11_Seed1,
       SEED2		       => M11_Seed2
);
    
    
-- Router/Module Connections --
   RI_R00(4)   <= RO_M00;
   AO_M00      <= AI_R00(4);
   DI_R00_P4   <= DO_M00;
   
   RI_M00      <= RO_R00(4);
   AO_R00(4)   <= AI_M00;
   DI_M00      <= DO_R00_P4;
   
   RI_R01(4)   <= RO_M01;
   AO_M01      <= AI_R01(4);
   DI_R01_P4   <= DO_M01;
   
   RI_M01      <= RO_R01(4);
   AO_R01(4)   <= AI_M01;
   DI_M01      <= DO_R01_P4;
   
   RI_R10(4)   <= RO_M10;
   AO_M10      <= AI_R10(4);
   DI_R10_P4   <= DO_M10;
   
   RI_M10      <= RO_R10(4);
   AO_R10(4)   <= AI_M10;
   DI_M10      <= DO_R10_P4;
   
   RI_R11(4)   <= RO_M11;
   AO_M11      <= AI_R11(4);
   DI_R11_P4   <= DO_M11;
   
   RI_M11      <= RO_R11(4);
   AO_R11(4)   <= AI_M11;
   DI_M11      <= DO_R11_P4;

-- Inter Router Connections --

   -- Router 00
   RI_R00(e_right_port_c)		<= RO_R01(e_left_port_c);
   RI_R00(e_bottom_port_c)	<= RO_R10(e_top_port_c);

   DI_R00_P3   <= DO_R01_P1;
   DI_R00_P0   <= DO_R10_P2;
   
   AO_R00(e_right_port_c)		<= AI_R01(e_left_port_c);
   AO_R00(e_bottom_port_c)	<= AI_R10(e_top_port_c);
   
   -- Router 01
   RI_R01(e_bottom_port_c)	<= RO_R11(e_top_port_c);
   RI_R01(e_left_port_c)   <= RO_R00(e_right_port_c);
   
   DI_R01_P0   <= DO_R11_P2;
   DI_R01_P1   <= DO_R00_P3;
   
   AO_R01(e_bottom_port_c)	<= AI_R11(e_top_port_c);
   AO_R01(e_left_port_c)   <= AI_R00(e_right_port_c);
   
   -- Router 10
   RI_R10(e_top_port_c)   	<= RO_R00(e_bottom_port_c);
   RI_R10(e_right_port_c)		<= RO_R11(e_left_port_c);
   
   DI_R10_P2   <= DO_R00_P0;
   DI_R10_P3   <= DO_R11_P1;
   
   AO_R10(e_top_port_c)   	<= AI_R00(e_bottom_port_c);
   AO_R10(e_right_port_c)		<= AI_R11(e_left_port_c);
   
   -- Router 11
   RI_R11(e_top_port_c)   	<= RO_R01(e_bottom_port_c);
   RI_R11(e_left_port_c)   <= RO_R10(e_right_port_c);
   
   DI_R11_P2   <= DO_R01_P0;
   DI_R11_P1   <= DO_R10_P3;
   
   AO_R11(e_top_port_c)   	<= AI_R01(e_bottom_port_c);
   AO_R11(e_left_port_c)   <= AI_R10(e_right_port_c);
   
-- Edges Connectivity --

	-- Router 00
	RI_R00(e_left_port_c) <= '0';
	RI_R00(e_top_port_c) <= '0';
	
	DI_R00_P1 <= conv_std_logic_vector(0, flit_size_c);
	DI_R00_P2 <= conv_std_logic_vector(0, flit_size_c);
	
	AO_R00(e_left_port_c) <= '0';
	AO_R00(e_top_port_c) <= '0';
	
	-- Router 01
	RI_R01(e_right_port_c) <= '0';
	RI_R01(e_top_port_c) <= '0';
	
	DI_R01_P3 <= conv_std_logic_vector(0, flit_size_c);
	DI_R01_P2 <= conv_std_logic_vector(0, flit_size_c);
	
	AO_R01(e_right_port_c) <= '0';
	AO_R01(e_top_port_c) <= '0';
	
	-- Router 10
	RI_R10(e_left_port_c) <= '0';
	RI_R10(e_bottom_port_c) <= '0';
	
	DI_R10_P1 <= conv_std_logic_vector(0, flit_size_c);
	DI_R10_P0 <= conv_std_logic_vector(0, flit_size_c);
	
	AO_R10(e_left_port_c) <= '0';
	AO_R10(e_bottom_port_c) <= '0';
	
	-- Router 11
	RI_R11(e_right_port_c) <= '0';
	RI_R11(e_bottom_port_c) <= '0';
	
	DI_R11_P3 <= conv_std_logic_vector(0, flit_size_c);
	DI_R11_P0 <= conv_std_logic_vector(0, flit_size_c);
	
	AO_R11(e_right_port_c) <= '0';
	AO_R11(e_bottom_port_c) <= '0';
    
end environment_arch;


